Static timing analysis (STA) is one of the pillars for verifying digital Very Large Scale Integrated (VLSI) circuit designs, and is widely used to predict the performance of the designs. STA is often used on very large designs for which exhaustive timing analyses are impossible or impractical in view of the number of patterns required to perform the analysis. State of the art static timing analysis tools make it possible to model designs with multiple timing modes and multiple corners only in a single environment. STA furthermore verifies that a VLSI circuit design performs correctly at a required frequency before it is released for manufacturing. When performing an STA, the design is represented as a timing graph; the points in the design where timing information is desired constitute the nodes or timing points of this graph, while electrical or logic connections between these nodes are represented as timing arcs of the graph.
With modern chip manufacturing technology scaling minimum device feature sizes to sub 65 nanometers, VLSI designs are increasingly getting larger in terms of size and complexity. Current day Application Specific Integrated Circuit (ASIC) designs contain several million gates while microprocessor designs can contain upwards of one billion transistors. While circuit simulation based timing analysis is most accurate, it is also run-time intensive, and is not practical to use it in a timing flow where timing runs are made regularly during the design cycle of a large chip. In essence, static timing analysis of such large circuits as a single flattened design is run-time prohibitive.
The aforementioned considerations have led to the concept of design partitioning and hierarchical timing. A given circuit is partitioned into several components labeled cores or units, which can be further partitioned into macros. A macro can simply be a collection of several to several thousand transistors or gates interconnected via wires designed to perform a certain task in the chip. In the simplest case, a macro can refer to a logic gate (e.g., logic AND gate). Macros are typically timed using accurate timing analysis techniques, (e.g. using transistor level timing tools with circuit simulation type accuracy in the case of microprocessor designs), and is followed by the generation of timing abstract models that reflect in a simpler form the actual timing characteristic of the macros. The latter step is termed timing macro-modeling or abstraction. The generated abstract of a macro captures its timing characteristic by the use of slew and load dependent tables to model the timing behavior of the logic. Delays and output slews (or waveforms) of timing arcs near the primary inputs (PI) of the macro are characterized as functions of input slew, while delays and output-slews of arcs closer to the primary outputs (PO) are characterized as functions of an output load, and sometimes a combination of both. This allows the generated abstract model to be used in multiple boundary condition (PI and PO) settings (i.e., wherein the input slews and the output loads during abstract usage differ from values during the generation of the abstract). Timing abstraction can employ techniques to reduce the size of the timing graph by performing graph pruning and arc compression. These techniques can reduce the number of timing arcs to be timed at the next level of hierarchy significantly. At the parent level of hierarchy, macros are typically represented by abstracts.
The timing abstraction process can be performed in a hierarchical fashion. A unit comprising several macro abstracts can itself be abstracted and used at the parent (core or chip) level. For ease of notation, the term macro will be used to denote any circuit component being abstracted, even if a unit containing other abstracts is being abstracted. The hierarchical timing approach enables fast timing analysis and productivity at the parent level (termed chip level for ease of notation in the present invention), since the abstract models facilitate fast timing analysis and allow re-use. The benefits are significantly highlighted when multiple instances of a macro are present at the chip level since timing analysis of the multiple instances can use the same timing abstract model instead of more accurate models being used for each instance. Timing abstracts are often referred to as intellectual property (IP) timing models. The abstracts can be used across different chip designs that need the same functionality provided by the abstracted macro. Essentially, abstracts provide a mechanism for sharing the same timing model across multiple instances of a macro within a design as well as across designs, and are therefore highly desirable for design productivity.
The impact of process variability in modern day chip design and manufacturing is significant in terms of the timing performance of a given VLSI circuit design. In addition to process variability, environmental variations (e.g. variations in voltage and temperature) contribute to the uncertainty in the design timing characteristics. Statistical Static Timing Analysis (SSTA) has subsequently emerged as a solution to address these issues and assess the impact of variations during timing analysis and optimization. In SSTA, timing quantities like delays and slews are treated as random variables with known distributions. Each timing quantity can be sensitive to multiple global sources of variability which are labeled parameters (e.g. voltage, temperature, channel length, transistor width, voltage-threshold, dopant concentration, and the like). Mathematically, the set of global parameters is denoted as: {X1, X2, X3, . . . , Xn}. A commonly used linear canonical form representation of a statistical timing quantity T is the following.
                    T        =                              t            0                    +                                    ∑                              i                =                1                            n                        ⁢                                          t                i                            ⁢              Δ              ⁢                                                          ⁢                              X                i                                                                        (                  EQ          .                                          ⁢          1                )            
In the model shown, t0 represents the mean value of the timing quantity T and denotes the nominal value of T in the absence of variability. ti denotes the sensitivity of T to a variation ΔXi of the global parameter Xi. To achieve commonality between parameters, ΔXi is denotes in sigma units instead of absolute parameter units (e.g. degree Celsius for parameter temperature). Typically, a −3 to +3 sigma range denotes the range of parametric variation. By way of example, if the expected temperature variation is between 0 degree Celsius and 100 degrees Celsius, the range can be denoted as a 6 sigma spread wherein −3 sigma, +3 sigma, and the nominal value (0 sigma) of parameter temperature corresponds to 0° Celsius, 100° Celsius, and 50° Celsius, respectively. If a timing quantity (e.g., delay) changes by 24 picoseconds due to temperature going from −3 to +3 sigma, the sensitivity of the timing quantity is computed as (24/6) or 4 picoseconds per sigma.
The operation voltage (V) value for a device (transistor or gate) strongly impacts the timing characteristics of the device. Typically, a given gate delay is smaller at a higher operating voltage compared to a lower operating voltage. In addition, the operating voltage also impacts the sensitivity of other parameters. As a result, the sensitivity ti corresponding to a process parameter Xi (e.g., dopant concentration) is a function of the parameter voltage (V) and can be denoted as ti(V). U.S. Application No. 2012/0117527 describes an approach to model the voltage dependence in ti(V) using a linear form: (ti0+tiVΔV). The term ti0 denotes a constant sensitivity of the timing quantity T to parameter Xi at the nominal condition of voltage (ΔV=0 sigma), while the term tiV denotes the cross-term sensitivity of T to both voltage and parameter Xi. In other words, tiV describes how the sensitivity of T to Xi changes with a change in voltage ΔV. Using the cited notation, the equation EQ. 1 can now be expressed as follows:
                    T        =                              t            0                    +                                    t              V                        ⁢            Δ            ⁢                                                  ⁢            V                    +                                    ∑                              i                =                                  1                  ⁢                                      (                                                                  X                        i                                            ≠                      V                                        )                                                              n                        ⁢                                          t                i                            ⁢              Δ              ⁢                                                          ⁢                              X                i                                              +                                    ∑                              i                =                                  1                  ⁢                                      (                                                                  X                        i                                            ≠                      V                                        )                                                              n                        ⁢                                          t                                  i                  ⁢                                                                          ⁢                  V                                            ⁢              Δ              ⁢                                                          ⁢                              X                i                            ⁢              Δ              ⁢                                                          ⁢              V                                                          (                  EQ          .                                          ⁢          2                )            
During statistical abstraction, statistical timing quantities and their sensitivities to all the parameters (including sensitivity to voltage) are captured for all the arcs in the timing graph of the macro. Traditionally, the mean value and sensitivity of any timing quantity captured in the abstract to either V or any other process parameter Xi is valid for the defined (sigma) range of chip operating voltage when the macro was abstracted. By way of an example, consider the statistical delay D of an arc inside a macro represented as follows:D=10+2ΔV+3ΔX1+0.4ΔVΔX1  (EQ. 3)
In the aforementioned model, the delay is 10 units at the nominal corner of V and Xi, that is, D(ΔV=0, ΔXi=0)=10. At a given ΔV value, for instance ΔV=+1 sigma, the sensitivity of the delay to ΔXi is {+3+(0.4×1)}=3.4 units per sigma. This suggests that a key assumption to using the delay model is to use the model where the voltage condition definitions are identical to the conditions when the macro was abstracted. By way of example, assuming that the nominal voltage condition when the macro was abstracted equals 1.05 volts, i.e., ΔV=0 sigma corresponds to V=1.05 volts. Further, assuming that the lowest operating voltage is 0.65 volts corresponds to ΔV=+3 sigmas, if the abstract is employed for another chip design where the nominal voltage is not 1.05 volts, the delay obtained from the abstract at the new nominal voltage (still 10 units) would be incorrect. Similarly, if the +3 sigma condition of the new design is not 0.65 volts, the sensitivity of delay to parameter Xi will be incorrectly computed as 3.4 units per sigma. Subsequently, a statistical timing abstract can traditionally be used for multiple instances within a chip only if all of the instances are on the same voltage domain as the domain used during generation of the abstract. The same applies for re-using an abstract across chip designs. The term voltage domain hereinafter will be used interchangeably with voltage islands as well.
Two embodiments make use of statistical abstracts across voltage domains for the same macro instantiation. In a first embodiment, abstracts can be generated for a macro per voltage domain. By way of example, if a chip has 2 domains, namely Vdd with voltage range 0.7 volts to 1.3 volts, and Vio with range 1 volt to 1.1 volts, two abstracts would need to be generated for each macro in the chip that can be instantiated in both domains. The first embodiment displays multiple disadvantages including increased abstract generation time, higher abstract storage requirements, and the limitation that voltage domains for new designs where the macro can potentially be re-used cannot be known in advance.
In a second embodiment, a single statistical abstract can be used for all domains by adding pessimistic guard-bands or margins. This approach typically suffers from pessimism, potential optimism, and the limitation that enough guard-bands may not be present for new designs with new voltage domains where the same macro can be instantiated. The limitations prohibit timing abstract re-use across designs, and negatively impact design productivity.
Referring to FIG. 1, a block diagram illustrates the intent to use a common abstract of a given macro instantiated at different voltage domains within and across designs. The macro M is instantiated twice in two domains, namely domain Vdd and domain Vio within Design B and once in a new domain Vdd* within Design B. The potential use of a single timing abstract without pessimistic margins for each of these three instantiations would aid design productivity and avoid overheads of maintaining multiple abstracts per domain for a given macro.
In more complicated cases, a chip can contain multiple voltage domains that are correlated instead of being independent, i.e., the operating voltage on each domain does not change independently. When multiple instances of the same macro are present on the domains and a path or timing test exists between the instances, leveraging the interdependence between the domains is crucial for accurate timing analysis.
Referring to FIG. 2, a block diagram is illustrated to show the paths between abstracts instantiated on multiple domains within the chip, showing the complexity of timing analysis with abstracts and multiple voltage domains. By way of example, if all domains in the figure are perfectly correlated, timing analysis considering any domain at a high voltage condition must consider all other domains at their corresponding high voltage conditions. However, if the domains are independent, multiple combinations of voltage domain conditions for each domain must be considered to obtain the potentially critical condition for timing analysis.
Accordingly, a need exists for sharing and re-using timing models considering voltage domains and their interdependence while taking manufacturing and environmental variations into account during a timing analysis of integrated circuit (IC) chips.